In modern digital computers, data is generally arranged in bytes, each of which has a number of bits. There are many situations where it is desirable to shift the bits in a byte to the right or to the left. For example, binary numbers may be stored in eight bit bytes. A binary number may be effectively multiplied by two by shifting the bits one position to the left. Thus, the binary number 00000100 can be multipied by two by shifting the bits one position to the left, thereby producing the binary number 00001000.
Data shifters can be divided into two classes, namely, clocked shift registers and matrix shifters. In clocked shift registers, data can be shifted one position in each clock cycle. Clocked shift registers are standard commercially available components.
Matrix shifters are also well known and commercially available. Matrix shifters are generally employed to shift data several bit positions in one clock cycle. In matrix shifters, there are data input lines, data output lines, and a plurality of shift control lines. The signals on the shift control lines indicate the number of positions that the data is to be shifted. For example, there may be three shift lines that have signals representing a binary number from zero to seven. Depending upon the value of the signals on the shift control lines, the data on the data input lines is shifted from zero to seven positions as it moves from the data input lines to the data output lines.
In some applications the data bits which overflow out of the high end of the shifter must be re-introduced into the low end of the shifter. Shifters which perform this function are generally known as barrel shifters, and the operation of introducing bits which overflow from one end on the shifter into the other end of the shifter is generally termed a "wrap" function. Barrel shifters can be implemented in the form of clocked shift registers or in the form of matrix shifters.
Many prior art matrix shifters, and in particular matrix shifters which use ECL technology, have been implemented by connecting together a plurality of multiplexers. Such matrix shifters require a substantial amount of wiring to interconnect the multiplexers into a matrix shifter.
Representative prior art matrix shifters which are formed by connecting together a plurality of multiplexers are shown in FIGS. 1A, 1B and 1C. FIG. 1A shows a prior art eight bit barrel shifter which includes three banks of 2 to 1 multiplexers A1, A2 and A3. Each bank of the multiplexers A1, A2 and A3 has eight positions, which receive two inputs and produce one output. Three select lines designated A-S0, A-S1, and A-S2 control the three banks of multiplexers and determine which input signals are gated to the output line at each bit position. Data bits on eight inputs D0 to D7 pass through the shifter to eight output lines F0 to F7. The position that the input bits D0 to D7 appear on the outputs F0 to F7 is determined by the signals on lines A-S0, A-S1 and A-S2.
Another prior art eight bit barrel matrix shifter implemented sing banks of multiplexers is shown in FIG. 1B. The circuit shown in FIG. 1B has one bank of 2 to 1 multiplexers B1 and one bank of 4 to 1 multiplexers B2. Three control lines B-S0, B-S1 and B-S2 determine how much shift takes place. Multiplexer bank B1 works identically to multiplexer A1 shown in FIG. 1A. Multiplexer bank B2 has 4 to 1 multiplexers wherein each bit position of the multiplexer has four inputs and one output. The particular input that is gated to the output is determined by the two control lines B-S1 and B-S2.
Yet another prior art matrix shifter which uses a bank of multiplexers is shown in FIG. 1C. The matrix shifter in FIG. 1C has only one bank of 8 to 1 multiplexers C1 which has eight positions. Each bit position in the multiplexer bank C1 receives eight inputs and produces one output. Which particular input is gated to the output is determined by control lines C-S0, C-S1 and C-S2.
As can be seen from FIG. 1A, 1B and 1C, the prior art ECL shifters have a substantial amount of wiring which directs the input bits to various bit positions in the multiplexers. Furthermore, additional logic (not shown in FIGS. 1A, 1B or 1C) is necessary to provide the appropriate fill bits for the bit positions at the side of the shifter from which data is shifted. For example, if data is shifted to the right, fill bits must be provided at the left side of the shifter, when the shifter is not used as a barrel shifter.